Many accelerators can speed up sparse computations, but in large clusters performance is often limited by communication, and software-based networking optimizations are inefficient. With NetSparse, we propose a set of new hardware mechanisms in SmartNICs and programmable switches that offload communication, eliminate redundant requests, combine multiple transfers into fewer packets, and cache data across racks. In simulations of a 128-node cluster, NetSparse accelerates sparse workloads by 38x compared to a single node, far surpassing the 3x speedup with software communication and reaching over half the performance of an ideal system with no network overhead.

Decision Trees (DTs) are ideal for in-network ML using programmable RMT switches owing to their hierarchical decisions and post-training interpretability. But traditional implementations only accommodate top-k features, limited by the small stateful memory in switches and deliver low classification performance. We present our vision of a partitioned DT inference architecture, SpliDT, where we delegate feature collection to subtree-level inference and reuse stateful resources over sliding windows of packets to scale far beyond top-k features. Preliminary results demonstrate that SpliDT inference yields Pareto frontier on F1 score vs number of stateful flows for many real-world security applications.

To support diverse data center environments and workloads, virtual switches (vSwitches) offer flexibility via multi-table programmable packet pipelines with flexible control flows and rely on caching packet lookups into a single table to deliver high performance. Maintaining a consistent view of this cache with the vSwitch pipeline under frequent updates is a hard problem owing to the nature of these pipelines: tables contain wildcard rules with priorities and it is difficult to determine how to reflect rule updates to individual cache entries. Therefore, with each update, the entire cache is "revalidated" in a brute force manner. This poster presents our vision for a new approach to cache consistency by framing the problem as an instance of Incremental View Maintenance (IVM), a long studied problem in large databases community where a view generated from a query is updated incrementally upon updates to the DB.

Gigaflow is a novel caching architecture designed for SmartNICs to accelerate virtual switch (vSwitch) packet processing. It leverages inherent pipeline-aware locality in vSwitches—defined by policies (e.g., L2, L3, ACL) and their execution order (e.g., using P4 or OpenFlow)—to cache rules for shared segments (sub-traversals) rather than full flows (traversals). These reusable segments improve cache efficiency (e.g., up to 51% higher cache hit rate) and capture more rule-space (up to 450x) compared to traditional Megaflow caching, all within the limited memory of modern SmartNICs.

Traditional Software-Defined Networking (SDN) literature abstracts the network into a centralized control plane and a simple, highly performant data plane. However, real-world SDN deployments—across virtual switches, hardware switches, 5G cores, and service meshes—rely on a third component: the slow path, which acts as an exception handler and provides an infinite-resource abstraction to the control plane. Though historically overlooked, we argue that the slow path is becoming a key bottleneck in modern data center networks and warrants its own dedicated accelerator.